1. Field
The disclosure relates to a printed circuit board and a method of manufacturing the same.
2. Background
A printed circuit board (PCB) is formed by printing a circuit pattern on an electrical insulating substrate by using a conductive material such as copper (Cu), and refers to a board right before electronic parts are mounted thereon. In other words, the PCB refers to a circuit board in which the mounting positions of the electronic parts are determined, and a circuit pattern connecting the electronic parts to each other is fixedly printed on the surface of a flat plate so that several types of many electronic devices are densely mounted on the flat plate.
Recently, as the electronic industry has been developed, demands for high functional and small-sized electronic components with price competitiveness and short delivery period have been increased. For this reason, PCB manufactures employ a semi-additive process (SAP) to satisfy the trend of slimness and high compactness of the PCB.
Meanwhile, a conductive via is formed in the PCB for electric conduction between layers. In addition, recently, a large via (which is also called bar via) having a size larger than a size of a normal bar has been developed by taking the heat dissipation performance of the PCB into consideration.
That is, in the case of a coreless substrate, the RF value, CW gain, CW output and CW efficiency may be determined according to the heat dissipation performance. In the case of PCB, a stack via is formed from an uppermost layer to a lowermost layer of a package in order to easily dissipate heat.
FIGS. 1 to 3 are sectional views showing a via structure of a PCB according to the related art. FIG. 1 shows a normal stack via structure according to the related art, FIG. 2 shows a rod-type via structure according to the related art, and FIG. 3 shows a pyramid-type via structure according to the related art.
Referring to FIG. 1, the PCB includes a plurality of insulating layers 1 connected with each other, inner layer pads 2 disposed between two different insulating layers, outer layer pads 3 formed on surfaces of an uppermost insulating layer and a lowermost insulating layer, and a plurality of vias formed in the insulating layers 1, respectively.
The vias include a first via 4, a second via 5, a third via 6, and a fourth via 7, which are spaced apart from each other by a predetermined interval. The first to fourth vias 4 to 7 are commonly connected to the inner layer pad 2 and the outer layer pad 4.
Referring to FIG. 2, the PCB includes a plurality of insulating layers 1 connected with each other, inner layer pads 12 disposed between two different insulating layers, outer layer pads 13 formed on surfaces of an uppermost insulating layer and a lowermost insulating layer, and vias 14 formed in the insulating layers 11, respectively.
The via 14 has a width wider than a width of a normal via. For example, the via 14 may have a width corresponding to the sum of widths of the first to fourth vias 4 to 7 shown in FIG. 1.
As shown in the bottom of FIG. 2, the via 14 may have a shape corresponding to a via hole by plating the via hole having a wide cylindrical shape with a metallic material.
Referring to FIG. 3, the PCB includes a plurality of insulating layers 21 connected with each other, inner layer pads 22 disposed between two different insulating layers, outer layer pads 23 formed on surfaces of an uppermost insulating layer and a lowermost insulating layer, and vias 24 formed in the insulating layers 21, respectively.
The vias 24 formed in the insulating layers 21 may have mutually different widths.
For example, the via formed in the central insulating layer may have a first width, the vias formed in upper insulating layers may have a second width wider than the first width, and the vias formed in the lower insulating layers may have a third width wider than the first width. At this time, the third width may be wider than the second width.
However, the rod-type via or the pyramid-type via has a volume relatively larger than a volume of a normal stack via as well as a long length, so a dimple may occur in the plating process.
FIG. 4 shows a via according to the related art.
Referring to FIG. 4, the via may have a concave shape D, in which a center region is lower than a peripheral region, and the concave shape is called a dimple phenomenon.
According to the related art, the plating process is performed several times in order to diminish the dimple phenomenon. However, if the plating process is performed several times, the lead time for the product may be increased.